Problems with interlock logic diagrams
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Could someone experienced explain the function of this circuit? There’s also the logic for interlocked shutdown; I wonder whether an OR gate should be used – why was an AND gate chosen in the logic diagram?
This diagram seems irregular and its logic is confusing. What was originally just a problem with an RS flip-flop and a delay has become complicated.
Why does M1 need to go back? I don’t know why
What this diagram shows is that when there is no DI signal input, pressing the reset button causes DO to keep outputting a signal; that’s all that can be observed. You need to think about it based on the meanings of DI and DO
The self-holding function – Conixen’s SIS often does this
The self-holding function is essentially the function of an RS flip-flop. Why is it designed this way?
Is that a reset? Is that to start it? It’s just a self-sustaining circuit, that’s all
SIS safety interlocks are generally designed in this way: the input DI serves as the interlock condition, where 1 indicates normal operation and 0 triggers the interlock. The reset button is effective when the interlock conditions return to normal 1, with the purpose of enabling manual confirmation and reset of the interlock when the conditions are normal. The AND gate was chosen because SIS is designed for fail-safe operation: it outputs 0 during interlocks and 1 under normal conditions, ensuring a safe state in the event of a wire break. For reference :)
The illustration shows a standard reset mechanism (the interlock can be activated again only after the interlock conditions return to normal and the operator performs a reset). RS flip-flop structure, suitable for applications requiring setting and resetting, with a concept of priority. When using an RS flip-flop to replace the reset structure, note the following: 1. The flip-flop pin is active at “1” ； 2. Flip-flops have a priority order (in typical fail-safe designs, the interlock conditions are connected to R, with R having priority over S). 3. RS flip-flops have default values (what is the initial default output of RS when both the R and S terminals are inactive?)
The M1 feedback is used to latch the reset signal. In some SIS systems, the RS flip-flops are unauthenticated and not allowed to be called.
The reset button only functions when the input DI condition is met; in other words, if the condition is not satisfied, pressing the reset button has no effect. Based on this logic, the input DI usually serves as a condition for shutting down the system as well as a condition for starting it up, and it depends on the overall logic diagram.