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Can anyone tell me why I made an error when doing Radfrac iteration? * * ERROR OUTSIDE LOOP TOLERANCE WAS SATISFIED BUT DESIGN SPEC ITERATION (MIDDLE LOOP) FAILED TO CONVERGE. I'm worried, but I still can't find the error?
Is there something wrong with the upper and lower limits specified in the design?
I don’t know what system the poster is simulating. I suggest that the poster try changing the convergence method on the Configuration page.
There may be something wrong with the variable range given in DESIGN SPEC ITERATION!
There may be a variable range in DESIGN SPEC, or the target value may not be reached at all. :)
I also encountered such a problem at the beginning. There is a second design rule in this book. You can enter both of them and run it. In the first design requirement, the distill rate you control cannot meet the purity requirements you designed. If the initial concentration is set to 0.2, it will converge.
Thank you for your enthusiastic attention. The above problems have basically been solved. It was because I did not initialize again after changing the parameter settings, and then it converged after initializing again and running. Then the friend upstairs asked, can the DISTIL analysis Tool mentioned in Chapter 2 of the book Distillation Design and Control Using AspenTM Simulation be found in plus?
It seems that there is no distl in the aspen11.1 version. It seems that it can be found in hysis. I don’t know what it looks like, haha.