Please explain in detail the output results of an RS flip-flop with set priority or reset priority
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This post was last edited by zhaohh3211 on 2009-6-15 09:06. Please explain in detail the output results of an RS flip-flop with set priority or reset priority If priority is given to setting, what is the output when both R and S are 1, and what is the output when both R and S are 0? If reset has priority, what is the output when both R and S are 1, and what is the output when both R and S are 0? No clear answer to this question can be found online; I hope experts can give some guidance.
This post was last edited by faol on 2009-6-13 23:26. With set priority, the original state is maintained when both R and S are 0; an output of 1 is generated when both R and S are 1. With reset priority, the original state is maintained when both R and S are 0; an output of 0 is generated when both R and S are 1. The author can understand the terms “reset priority” and “set priority” after reading them five times... With set priority: S 0 1 0 1, R 0 0 1 1 → OUT remains 1 0 1. With reset priority: S 0 1 0 1, R 0 0 1 1 → OUT remains 1 0 0
I used to understand it in the same way as well. However, when both S and R are 0, it seems that the output should be 0 rather than remaining unchanged. Therefore, when creating interlock logic diagrams, we usually define this ourselves first; otherwise, it’s difficult to meet the process requirements. ESD manufacturers also understand that when both S and R are 0, the output is 0 ； I hope more people will explore it!
If priority is given to setting, the output is 1 when both R and S are 1; it remains unchanged when both R and S are 0. If priority is given to resetting, the output is 0 when both R and S are 1; it remains unchanged when both R and S are 0
2# faol The friend above explained it very correctly
Just check the help documentation by yourself, ah! If it doesn’t work, just pull in a few modules to test it yourself! I didn’t understand it either before, but it got much better after I tried it myself!
I had also studied some things related to digital electronics before, and that included information on flip-flops; however, it focused on the RS basic flip-flop and the RS master-slave flip-flop, with the constraint that R and S cannot both be 1 at the same time. I looked at an RS flip-flop in one of our current interlock diagrams; it wasn’t specified which type, but it doesn’t allow RS to be 1 at the same time
It’s the same on our company’s design drawings as well; the RS priority determination is quite ambiguous. As mentioned above, when RS is also 1, the state is indefinite.