What does DT mean in the interlock logic diagram?
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Hello, sea friends! In the logic diagram of the SIS system, there is a type of delay called DT. What does it mean? I am a process engineer, and I hope those who know about this can explain it to me. Thank you!
DT I remember is the output delay at the rising edge, while DI is the output delay at the falling edge
The DT delay time is for reference only
dt refers to the number of seconds that pass after an interlock is triggered before the next level of interlock is activated