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Take a look at this logic diagram; this is the SIS logic diagram

2018-09-16View Original

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My question is: is this RESET reset function related to an RS flip-flop? Priority is given to reset, right? When IN is 0 and becomes 1, OUT remains the same. When IN is 1 and ID is 0, OUT becomes 1. When IN is 0 and ID becomes 1, OUT becomes 0. When IN becomes 0 and ID remains 0, OUT becomes 0. I feel like I’m getting confused! ! ! ! This doesn’t correspond to the truth table of an RS flip-flop either. What’s going on?
Reply #22018-09-17
It doesn’t seem to be the RS flip-flop approach.
Reply #32018-09-17
RS doesn’t have any judgment based on rising or falling edges; yours isn’t that
Reply #42018-09-17
It seems it’s at least not an RS flip-flop; what should be used for solving this as well?
Reply #52018-09-17
Why is it so complicated? I feel like the ID is just a reset button. When the ID becomes 1, OUT is reset to 0; otherwise, it follows the IN value.
Reply #62018-09-17
You’re wrong; this is SIS. When IN is 0 and ID0 becomes 1, the output is 0; it is only 1 when IN is 1 and ID0 becomes 1
Reply #72018-09-17
All of SIS’s approaches are the opposite of those in DCS
Reply #82018-09-17
I heard this expression for the first time……
Reply #92018-09-17
It appears to be a 0 interlock logic: the ID corresponds to the reset button; once interlocked, the output remains at 0, and the interlock state cannot be reset. It’s just my personal guess, haha

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