Question about interlock logic diagrams
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Dear teachers, when designing interlock logic diagrams, is it possible to specify that when both conditions A and B are met, the logic output of B should be triggered first? The logical outputs of Condition A and Condition B are different.
:Lol, it can’t be shown on the logic diagram; just add an explanation.
This post was last edited by jlshnlhj on 2022-3-16 21:38. Computers scan point by point; for A and B, what time interval is required between them for A and B to be considered satisfied simultaneously? Is B preferred within 1 scan cycle? That delays signal A by 1-2 scan cycles. The A delay time can be set using the TON or TP module.
The output of B can be used as a normally closed contact for interlocking A; the program executes B first and then A.
This is not easy to represent using an interlock matrix, but it is easier to represent using control logic. First, check B; if B meets the conditions, execute and output B. Otherwise, check A; if A meets the conditions, execute and output A. No AND or OR needed.
Can proper use of set priority and reset priority meet your needs?