The issue of triple redundancy in SIS systems
Thread Content
The SIS system features triple TMR redundancy; all IO cards have triple redundancy, while the power supply and communication cards have 1:1 redundancy. How is it achieved?
For this suggestion, it’s better to look up the system architecture schematic of TRICON; it’s quite intuitive.
The so-called triple redundancy does not involve multiple cards; rather, it means that one card contains three signal circuits. Each card has one channel for the incoming signal; the three internal electronic circuits handle the signal processing, which is equivalent to a three-way voting mechanism for system processing. The power supply and communication cards feature 1:1 redundancy
According to an expert from hcbbs, in GE’s MARK IV/GMR systems and Woodward’s MircoNet systems, the CPU and IO are placed in three separate racks each……
What we usually talk about most is triple redundancy for CPUs, while triple redundancy for I/O cards is quite rare. If a single signal enters one card and is then processed via three signal processors within that card, this doesn’t really count as triple redundancy either
A certain expert from HCBBS also said that with Triconex, HIMA, Yokogawa, and ICS, there is the issue of all CPUs being on one backplane