I hope an expert can help resolve some doubts I have regarding RS flip-flops in the interlock logic diagrams of SIS systems
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The last edit to this post was made by sb5436 on 2017-7-31 at 10:08. 1. Why is a NAND gate used at the S input of the RS flip-flop in Figure 1 compared to Figure 2? Won’t the value at the S input become 0 after using a NAND gate?； ②What does the small circle in front of the OR gate’s input mean? ； ③Why do both Figure 1 and Figure 2 use the Q non-terminal output? Doesn’t the textbook state that it should be the Q terminal output? 2. Can Figure 2 be understood in this way: when the trigger terminal S is 1, the output terminal is immediately set to 1; thereafter, regardless of the state of S, the output terminal remains at 1 until the flip-flop is reset, that is, when the reset terminal R becomes 1, at which point the output terminal changes to 0 and remains there until S resets the flip-flop again? 3. In university electrical engineering, I learned about the two basic RS flip-flops composed of NAND and NOR gates. When using them in practice, I found that they differ significantly from the RS flip-flops used in SIS systems; this caused me a lot of confusion. I hope for some guidance!
This post was last edited by superme84 on 2017-7-31 at 12:30. Electrical engineering in universities is taught using positive logic, whereas this SIS employs negative logic for programming and configuration; both inputs and outputs use \"fail-safe contacts\", meaning a value of 0 indicates operation, while 1 indicates maintenance of the current state. Points to note: 1. For the input – low pressure in the main gas pipeline, the trigger value is 0 rather than 1; therefore, an inversion operation is required to activate the RS flip-flop. 2. What does adding a small circle mean? It means inverting the signal; since the reset button triggers an action of type 1, inversion is used to ensure consistency with the logic related to low pressure. 3. The output is a 0 action, so the Q non-terminal output is used.
The answer above is correct; the main difference in the logic between SIS and DCS is that in SIS, 0 represents a valid value, while in DCS, 1 represents a valid value. The most significant consequence of this difference is that, when there is a power outage, the output signal from SIS becomes all 0s, as there is no power available. As a result, all the necessary actions are taken, ensuring absolute safety in fault conditions. In contrast, with DCS, the signal is 0 when power is lost, and everything remains in a non-active state, thereby ensuring continuous production
In the SIS safety interlock system, elements such as the low-low pressure button and the bypass circuit are always under voltage. For example, when a low-low alarm occurs, the value becomes 0; subsequently, NOT becomes 1, causing the RS flip-flop to be set to 1. When the low-low condition is no longer present, pressing the reset button changes the value to 0, and after inversion it becomes 1. I’m a bit confused here – I think the inverted signal from the reset button should be connected directly to the RS flip-flop, rather than going through an OR operation followed by inversion before being connected to the RS flip-flop
Take a close look at the interlock logic diagram and you’ll understand.
Is the reset button normally 0, and becomes 1 when pressed?
I would like to ask about the interlock logic relationships on the chemical operator page. And/or: An action is taken only when all two or more conditions are met. . Or, for two or more conditions, an action is taken as long as one of them is met. Is this the correct way to understand it? ? (Why did my colleague say I got it wrong?)
This post was last edited by jlshnlhj on 2022-6-5 18:56 with the caption: “Action is taken only when all conditions are met.” Saying “action” is inaccurate. Negative logic is incorrect, and it’s reversed as well. Generally, it’s all 1, with 1 appearing. Whether it’s positive or negative logic. As for whether it’s a 0 or a 1 action, that’s another matter.