Consultation on interlocking
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I would like the experts to help explain this logic. It should be that the cut-off valve shuts off as long as any one of those conditions is met; why use ‘and’? Also, what does TRIP mean? Thank you everyone
This diagram is incomplete; on the left side, there should be the valid states for each signal (0 valid or 1 valid), and on the right side, there should be indication of whether it shuts down when powered on or when power is lost.
No, it’s displayed in the SIS system; it’s not easy to understand
Modern SIS systems are required to be fail-safe, meaning they remain powered in normal operation but lose power when interlocked. Fail-safe systems use negative logic, that is, 0 means interlock while 1 means normal operation; therefore, an AND gate is used. Also, TRIP means getting out of the vehicle or stopping it.
“And” means that all conditions must be met simultaneously. Ask the process team about this
So if we don’t look at the design drawings, how can we know whether this has intrinsic safety, and how can we assess this logic? Thank you, I don’t understand
Current regulatory standards require that SIS designs be fail-safe. As for the judgment, it’s simple: look at the last element in the interlock – is it an AND gate or an OR gate? If it’s an AND gate, then it’s a type 0 interlock, which belongs to negative logic and is fault-safe ； If it is an OR gate, then it represents a 1 interlock, which falls under positive logic.
There are also interlocks that only activate when all conditions are met; in that case, it should be an \"and\"
When it is said that all the conditions are met, it means that interlocking does not occur only when all conditions are satisfied; interlocking takes place as long as one condition is not met. Rather than saying interlocking occurs only when all conditions are met.
This diagram is merely a schematic shown on the host computer. If AND logic blocks are used internally, then the trigger condition must be 0; if OR logic is used, the trigger condition must be 1. The key is to see how the logic is structured on the slave computer
This is likely the logic implemented in the SIS; many SIS systems use inverse logic, with 0 being used to trigger interlocks. As you can see, if even one of the conditions before AND is 0, then the output of AND will be 0, which triggers the disconnection of power to the valve.