Let's see if there is any problem with this interlocking logic.
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I think there is a problem. The valve at the back is 0 interlock. Why is the previous condition 1 interlock? Why not make it 0 interlock?
Do you have the final say on the shutdown signal? Don’t you have to look at the electrical signal?
In fact, it doesn't make much sense to choose 0 or 1 for the front-end logic. If you choose inverse logic, then you have to invert it later, and then the OR logic becomes AND logic. What's the difference? The latter part is the important part, fail-safe logic must be implemented
This post was last written by wx_Wang81529 edited on 2022-8-10 15:56 What signal does electrical require? What does it have to do with me losing power to the relay?
The 0 interlock at the back is fail-safe, but isn’t it counter-logical?
I think you should use AND zero logic instead of OR. Why didn't I see the bypass? If there is a problem with the relay, the interlock will not be triggered.
Inverse logic refers to the implementation of programming configuration in the controller, such as DCS, PLC, and SIS. Fail safety is a requirement for the hardware of the actuator, such as FO or FC. Of course, it must be implemented in conjunction with the normally open and normally closed functions of the output relay. Ultimately, it is necessary to achieve a relay power-off or circuit power-off to ensure that the valve is in a position that makes the process safe. Therefore, valve selection is key. Everything else is easy to implement.
The relay is connected normally open. When the interlock is activated, the relay contacts are disconnected, or when the relay fails, the contacts are disconnected, which can ensure that the valve loses power. Why not?
No problem, 0 interlock is a fail-safe mode and meets the requirements. The previous input of 0 or 1 has no effect.
This post was last written by wx_Wang81529 edited on 2022-8-11 09:09 If there is 0 interlock in front, it is negative logic, and if there is 1 interlock in front, it is positive logic, right? Positive and negative logic is only related to the previous detection part. The following execution part is 1 or 0. It is only the difference between fail-safe and non-fail-safe, not the difference between positive and negative logic, right?
There is no need to worry about this, just make sure that the entire interlocking logic is correct.