Take a look at this SIS interconnection diagram and discuss how to control it
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I have received the SIS drawings. I’m not sure if there are any issues with the layout; please discuss any problems you notice in the drawings
1. What is it and what are its functions?
1. What is it and what are its functions?
2. Is it an AND gate or an OR gate? I’ve never seen it drawn this way. 3. Is it true that in sis, everything uses reverse logic? Normally, 1 should reset to 0. 4. What does this mean? 5. Can everyone explain based on this diagram how control is achieved, along with the reasons and outcomes?
This post was last edited by budaoweng123 on 2017-9-26 at 11:46. 1 represents NOT, that is, it outputs the inverse of the input signal; 2 should be an AND gate. As for why it’s drawn like this, it’s because the design firm you hired is pretty poor. The first page of a general interlock logic diagram usually contains a legend for explanation. The 3SIS logic is generally inverse, meaning that a value of 0 is output when the interlock setpoint is reached; however, it’s clear that the logic in this screenshot is positive. As for whether the output from the RS flip-flop is used in other interlocks, it’s difficult to give a definite answer based on just one screenshot. The pixels of the 5 images are too poor; they are blurry and not clear to see.
There are no legends at all; you have to guess what the damn pictures represent