Experts, please help explain the following interlock logic
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This post was last edited by 20057614 on 2019-5-2 at 23:16. Could someone help me explain this sequential logic in the diagram? I don’t understand it: Q
1 is a power-off delay timer; as can be seen from the waveform diagram, when A has a signal, B also has a signal. Once A loses power, B stops sending a signal after a delay of t time. However, if A does not lose power for more than t time, B will not activate. 2 is a power-on delay timer: when A has no signal, B also has no signal. B starts to send a signal only after A has been powered on for more than t time. If A has been powered on for less than t time, B will not be activated. 3 is pulse output: as long as A is powered on, regardless of the duration, B will be powered on for t time
Thank you so much for your guidance; it all became clear right away. I’m extremely grateful!
They are shutdown delay, startup delay, and pulse respectively