Regarding the interlock logic diagram RS flip-flop
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I’ve never really understood how to use RS flip-flops – when to use them and when not to. Sometimes it triggers on 1, sometimes on 0; it’s quite confusing
Same question: it always appears in logic flow diagrams, and I can’t figure it out
Normally, it is triggered by 1. Fail-safe mode is 0 trigger
RS flip-flop or SR flip-flop? RS reset priority or SR set priority?
It’s hard to say; let’s use the previous diagram. For this diagram, I personally think it can be achieved without using triggers