Seeking advice on DCS logic diagrams
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Hello everyone, I’m facing a few issues with the instrument DCS logic diagram and would like to ask for your help. The problems are as described in the image. It also includes process diagrams; I’m mainly confused about the use of NAND gates and RS flip-flops...
1. That 1 indicates a high level, which is 1, when a signal is sent； 2. The non-pin of the NAND gate is not used because no interlock is required during debugging or manual operation ； Chain input and chain reset are not mandatory, but without them, debugging becomes very difficult
Then what is the purpose of placing an RS flip-flop behind the NAND gate?
The RS flip-flop is used to reset interlock commands
SR flip-flops can be either reset-priority or set-priority; for example, if it is set-priority, the output will remain at the set level even if it is reset to 1. Additionally, interlocks are generally fail-safe in nature, meaning they are at 1 under normal conditions and at 0 in the event of a fault.
Thank you! “Does the “Interlock Reset” signal output “0” when a fault occurs and Q is not active? So at that time, when the interlock value is reached and output is generated, are the input values S=1 and R=0?