What is the output when all the input terminals of the SR flip-flop in the logical interlock diagram are 0?
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What is the output when all the input terminals of the SR flip-flop in the logical interlock diagram are 0? In previous implementations of interlocks, the SR input was always 0, meaning there were no interlock conditions and no one pressed the reset button. In such cases, it was assumed that the output would remain at its previous state; in other words, the process parameters reverted from the interlock values to normal values, and the valve continued to remain in its interlocked state until someone pressed the reset button, at which point the valve returned to its normal position. But after looking up information on digital circuits online, it says that in this case the output state of the flip-flop is uncertain?
When all the input terminals of an SR flip-flop are 0, its output state is uncertain. This is because an SR flip-flop is an asynchronous circuit, its output state depends on the input level states and the historical states, which are unknown. In practical engineering applications, to ensure the reliability and stability of the system, additional circuit designs are required to ensure that the output state remains stable at a specific value when the input state is undefined, thereby avoiding unexpected failures. -
When all are 0, it remains in the last state; for example, if at that time S=1, R=0, Q=1, then S=0, R=0, Q=1
Well, the RS flip-flop is what confuses beginners the most when they first start learning. But we have a good solution. When memorizing, don’t remember 0 and 1 – if you remember both 0 and 1, your mind will become a mess. Input, indicate valid or invalid; 1 means valid, 0 means invalid ； Then it outputs 1 and 0, that is, there is an output or no output. When R (reset) is active, there is no output ； When S (the set is given) is valid, there is an output. If all RS values are valid, then which one has priority and which one is truly valid? ； If RS is invalid, the output remains unchanged. Finally, to answer the original poster’s question: if RS both yield no effect and the output remains unchanged, what does that mean? It means that the output can only be in two states – either 1 or 0; there is no third state possible. So it’s easy to understand why the output remains unchanged – it stays as it was before. There’s no need to consider quantum mechanics; the device already has a definite state, and if RS both result in 0, then that’s the outcome.