How to design a simple interlock for the Zhejiang University Zhongkong JX300X as shown in the figure below?
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It only involves some simple operations; I haven’t received any training on the Zhejiang University Zhongkong JX300 system. How do I handle simple logic tasks? Please give me some advice. . .
Define the hard points in the IO module, the soft points in the byte setting, and then in the logical configuration, bring in the corresponding logic blocks and functional modules, connect the wires, and carry out debugging.